1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and particularly, to a semiconductor device including a MOS transistor and method of manufacturing the same.
2. Description of the Background Art
The allowable value to alignment mismatch (alignment margin) of the constructions in manufacturing steps is decreased as semiconductor devices are miniaturized. This is an obstacle to high integration of semiconductor devices. In order to facilitate integration without being restricted by the alignment margin, it has been examined that the semiconductor elements constituting a semiconductor device are made to have such a structure as may not be subject to disadvantages in the event of an alignment mismatch.
For example, there is such a method of making a MOS transistor have a self align contact structure (hereinafter referred to as SAC structure) in a memory part where high integration is especially required in semiconductor devices.
FIG. 31 gives an one example of SAC structure. In FIG. 31, two gates GT are disposed a predetermined distance apart on a silicon substrate 101. The gates GT comprise a gate oxide film 102 disposed on the silicon substrate 101, a gate electrode 103 on the gate oxide film 102, an upper nitride film 104 on the gate electrode 103, and a sidewall nitride film 105 disposed such as to make contact with the side faces of the upper nitride film 104, gate electrode 103 and gate oxide film 102. A source/drain layer SD is disposed in the surface of the silicon substrate 101 lying on both sides of the gate GT.
An interlayer insulating film IZ formed from a silicon oxide film is disposed such as to cover the two gates GT, and a contact hole CH penetrating the interlayer insulating film IZ is disposed such as to reach the source/drain layer SD between the gates GT. A conductor layer CL is buried in the contact hole CH.
Since the gate electrode 103 is covered with the upper nitride film 104 and sidewall nitride film 105, it is possible to prevent the upper nitride film 104 and sidewall nitride film 105 from being removed in forming the contact hole CH. In the event of a contact hole dislocation, it is possible to prevent the gate electrode 103 from being exposed, and no short-circuit is developed between the conductor layer CL and gate electrode 103. Thereby, the contact hole CH can be formed without being restricted by the alignment margin. In this case, the opening size of the contact hole CH is determined in a self-aligned manner by the distance between the gates GT, and hence it can be called "self align contact."
Accordingly, the employment of the SAC structure allows it to be less subject to the restriction of alignment margin, and thus facilitates integration. Therefore, the SAC structure is useful with the memory part in which the distance between the two gates is progressively shorter. Unfortunately, the SAC structure is not applicable to the logic part.
Specifically, in the logic part, the resistance value is lowered for attaining high speed operation by silicide structure that a silicide layer is formed in a self-aligned manner on a gate electrode and on a source/drain layer of a MOS transistor. Whereas in the SAC structure, an upper nitride film is formed on a gate electrode, and it is impossible to form a silicide layer on the gate electrode, thus failing to form a MOS transistor of SAC structure in the logic part.
Conventionally, such a method of forming a silicide protection film comprised of a silicon oxide film has been employed in order to prevent that a silicide layer is formed on a gate electrode of a protection circuit for the protection of a main circuit from surge voltage, and on a source/drain layer in the vicinity of the gate electrode, thereby avoiding the current concentration due to irregularities of the crystal particles in the silicide layer.
FIG. 32 gives an example of formation of a silicide protection film. As shown in FIG. 32, gates GT1 and GT2 are disposed a predetermined distance apart on a silicon substrate SB.
The gate GT1 comprises a gate oxide film OX disposed on the silicon substrate SB, a gate electrode GE on the gate oxide film OX, and a sidewall oxide film SW disposed such as to make contact with the side faces of the gate electrode GE and gate oxide film OX.
The gate GT2 comprises a gate oxide film OX disposed on the silicon substrate SB, a gate electrode GE on the gate oxide film OX, a silicide layer SF on the gate electrode, and a sidewall oxide film SW disposed such as to make contact with the side faces of the gate electrode GE, silicide layer SF and gate oxide film OX.
A source/drain layer SD is formed in the surface of the silicon substrate SB lying on both sides of the gates GT1 and GT2, and a silicide layer SF is disposed on the source/drain layer SD.
Note that a silicide protection film SP is formed on the gate GT1 and on the surface of the source/drain layer SD lying in the vicinity of the gate GT1, and no silicide layer SF is disposed on the gate GT1 and on the surface of the source/drain layer SD in the vicinity of the gate GT1.
In this manner, it is avoidable that a silicide layer is formed on the gate GT1 and on the source/drain layer SD in the vicinity of the gate GT1, by virtue of the presence of silicide protection film SP. It is not impossible, therefore, that a MOS transistor of SAC structure and a MOS transistor of silicide structure are provided together. However, the manufacturing steps is complicated by selective formation of a silicide protection film SP, and restriction is imposed on the distance between the gates, because of the necessity of forming the silicide protection film SP. Consequently, hitherto no attempts have been made to construct so that a MOS transistor of SAC structure and a MOS transistor of silicide structure are provided together in both memory part and logic part. This is true for circuit parts other than the memory part and logic part.
To meet demanding requirements of high integration and high speed operation of semiconductor devices in recent years, the inventors recognized the necessity of a technique of providing together a MOS transistor of SAC structure and a MOS transistor of silicide structure when they attained such a technical thought of employing a MOS transistor of silicide structure in a memory part and a MOS transistor of SAC structure in a logic part.